Routinely now it is possible to generate an internal clock signal in a memory chip that is synchronized to an external clock signal, as in U.S. Pat. No. 6,340,904, entitled “Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal” of Troy A Manning of Micron Technology, Inc., Boise, Id. Another of Troy Mannings patents, U.S. Pat. No. 6,338,127,entitled “Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same” filed Aug. 28, 1998 and issued Jan. 8, 2002 describes a computer chip related system that adaptively adjusts the phases of a plurality of internal clock signals, each respective internal clock signal causing a corresponding latch to store a digital signal responsive to the respective internal clock signal. The system includes a plurality of clock control circuits, each clock control circuit controlling the phase of a respective internal clock signal relative to a corresponding external clock signal responsive to a respective phase command signal. Generally, in computer systems of the past represented by IBM's S300 and z900 systems, the clock frequency and phase relationship are fixed among the computer's Central Processor (CP), Storage Controller (SC), Main Storage Controller (MSC) and Memory and memory adjusts to the signals providing this fixed relationship. This design strategy simplifies the design implementation and debug procedure, but has certain limitations resulting which can make it impossible to optimize efficiency of particular elements of the computer system in order to maximize the system performance.